Logic Timing

Propagation, Setup, and Hold Times

Real-world logic components have propagation delays. Combinatorial logic components (logic gates) have specified delays from the time an input changes until the output changes. And, synchronous logic components such as D-Flip-Flops have a specified delay from the clock edge that triggers it to when the output changes. Propagation delay includes not just the time for logic signals to work their way through the device but also the time for the output to transition to the appropriate valid logic level.

Synchronous components also have requirements around the timing of input signal changes to clock edge. These are called setup and hold times. Setup is the minimum time before clock edge by which all synchronous inputs must have completed their transitions and be at a valid logic level. Hold is the minimum time after clock edge for which all inputs must be held stable at valid logic levels.

Setup Time: Minimum time for inputs to be stable before clock edge

Hold Time: Minimum time for inputs to remain stable after clock edge


Another important timing specification of logic devices is skew. Basic logic devices are available as multipacks – many devices in package (integrated chip). The propagation delay through each of the devices in a package will not be exactly the same. The maximum difference in propagation delay between the devices in a package is called skew, or more specifically called channel to channel skew, device to device skew, or intra-part skew. Even greater skew exists between devices in different parts; this is called part to part skew.

Device to Device Skew: Max propagation delay difference between devices within a multi-device part

Part to Part Skew: Max propagation delay difference between devices across all parts.


Let’s look at the Timing Requirements of a real part, the Texas Instruments SN74LVC1G80 Single Positive-Edge-Triggered D-Type Flip-Flop shown below.

D-Flip-Flop Timing Requirements
D-Flip-Flop Timing Requirements